Semiconductor & Electronics
Patent Attorney in Austin, Texas
An Austin patent attorney with hands-on semiconductor industry engineering experience — backed by a physics degree and 17 years of USPTO patent prosecution.
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Seven Years on the Fab Floor — What That Means for Your Patent
I want to be specific about my semiconductor engineering background because the specifics matter for understanding what I actually bring to semiconductor patent prosecution — not the general credential of having worked in the industry, but the specific technical experience that shapes how I engage with semiconductor patent claims.
I worked for over seven years as a manufacturing process engineer in the semiconductor industry, specializing in laser lithography — the photolithographic process that defines the nanoscale features on integrated circuits. Laser lithography sits at the physical core of semiconductor fabrication: the interaction of deep ultraviolet radiation with photoresist chemistry, the optical system design that determines resolution limits, the process control algorithms that maintain feature dimension tolerances across wafers, and the yield engineering that translates process parameters into device performance. Working in this environment gave me a working understanding of semiconductor physics, optics, process control, and manufacturing integration that predates my legal career and that informs how I engage with semiconductor patent claims at an engineering level.
What this means practically for semiconductor clients is that when you describe your circuit architecture innovation, your novel fabrication process, or your device structure improvement, I understand what you are describing — not as a sophisticated technical briefing that I interpret through a legal lens, but as an engineer discussing a technical problem with a colleague who has worked in the same environment. That starting point changes the quality of the prior art search, the technical accuracy of the specification, the engineering precision of the claim language, and the credibility of the prosecution arguments — all the factors that determine whether a semiconductor patent provides genuine competitive protection or just legal formality.
Integrated Circuit Architecture Patents — Claiming the Innovation, Not the Implementation
Integrated circuit architecture patents — covering novel circuit topologies, memory array organizations, processor microarchitectures, and analog and mixed-signal circuit designs — represent some of the most commercially significant patents in the technology economy. The companies that hold strong IC architecture patents can extract significant licensing revenue across the semiconductor ecosystem and can establish competitive positions that persist for years beyond any individual product cycle.
The central challenge in IC architecture patent prosecution is claiming the innovation at the right level of abstraction — broad enough to cover the commercially relevant implementations of the inventive concept, including implementations that differ from the specific version the inventor built, but narrow enough to distinguish over the dense prior art landscape of prior circuit designs. An IC architecture patent that only covers the exact transistor topology the inventor designed provides minimal competitive value — a competitor can modify that topology in ways that are technically equivalent but formally outside the claim scope. An IC architecture patent that claims the underlying circuit principle at a level that captures all technically equivalent implementations provides genuine competitive protection.
Identifying that right claim level — and drafting claims that achieve it while surviving USPTO examination — requires understanding the circuit architecture at an engineering level. What is the underlying technical insight? What design choices reflect that insight versus what choices are arbitrary implementation details? What alternative implementations of the same underlying concept would a skilled circuit designer naturally arrive at? My circuit engineering background from semiconductor manufacturing — working with the transistor-level implementations of process control circuits and understanding the design-process interaction that determines circuit performance — informs how I make these claim scope judgments in IC architecture patent prosecution.
Semiconductor Fabrication Process Patents — Protecting the How
Semiconductor fabrication process patents — covering novel deposition processes, etch chemistries, lithography techniques, planarization processes, and integration schemes — represent a category of IP that is particularly resistant to reverse engineering and particularly valuable for companies whose competitive advantage lies in manufacturing process know-how rather than (or in addition to) circuit design innovation.
My laser lithography engineering background is directly relevant to a significant category of semiconductor fabrication process patents. Photolithography — specifically deep ultraviolet lithography, EUV lithography, and the various resolution enhancement techniques that extend lithographic patterning capability — is one of the most patent-active areas of semiconductor process development, with major players including ASML, Applied Materials, Lam Research, and their competitors continuously filing patents on incremental and fundamental improvements to lithographic process capabilities. Having worked in lithography process engineering gives me the ability to evaluate these patents and competing innovations with technical credibility that practitioners without process engineering experience cannot match.
Beyond lithography, semiconductor fabrication process patents cover CVD and ALD deposition processes for advanced dielectric and conductor materials, plasma etch processes for high-aspect-ratio feature definition, CMP planarization processes for global and local planarity control, and the integration schemes that combine these unit processes into manufacturable device fabrication flows. Each of these areas requires specific domain knowledge to identify what is novel, conduct effective prior art searching in the technical literature where process innovations are documented, and draft claims that capture the genuine inventive contribution at a level that survives USPTO examination.
The competitive significance of semiconductor process patents is particularly high in the current environment of increasingly concentrated chip manufacturing — with a small number of leading-edge fabs controlling the most advanced process nodes, and process technology differentiation representing a major competitive dimension between those fabs and their customers' design houses.
Power Electronics, MEMS, and Specialty Semiconductor Devices
Beyond the mainstream logic and memory semiconductor categories, Austin's semiconductor ecosystem includes significant activity in power electronics, MEMS devices, photonic integrated circuits, and specialty semiconductor applications for automotive, industrial, and IoT markets — each category with its own distinct patent landscape and prosecution dynamics.
Power electronics patents — covering novel power conversion topologies, gallium nitride and silicon carbide device innovations, advanced gate driver designs, and wide-bandgap semiconductor applications — are among the fastest-growing patent categories in the semiconductor space, driven by the electrification of transportation, the growth of renewable energy infrastructure, and the power efficiency demands of data center computing. The physics of wide-bandgap semiconductor devices — specifically, the interaction of high electric fields with GaN and SiC material properties — draws directly on semiconductor physics that my physics education and semiconductor engineering experience address. I approach power electronics patent prosecution with the material science and device physics understanding that these technically demanding inventions require.
MEMS device patents — covering novel sensor structures, actuator mechanisms, fabrication processes, and packaging approaches for microelectromechanical systems — sit at the intersection of mechanical engineering, semiconductor fabrication, and electrical measurement that requires cross-disciplinary technical understanding to address effectively. The same lithographic patterning and thin-film deposition processes I worked with in semiconductor manufacturing are the foundational processes of MEMS fabrication — which means my process engineering background provides directly applicable technical context for MEMS patent prosecution.
Photonic integrated circuit patents — covering silicon photonics platforms, III-V semiconductor optical devices, photonic crystal structures, and optical interconnect technologies — combine my optics background with my semiconductor engineering experience in a way that is uniquely applicable to this technically demanding and commercially significant category. The optical physics of waveguide propagation, mode coupling, photon-electron interaction in semiconductor materials, and the fabrication processes that implement photonic structures draw directly on both my physics education and my experience working with optical systems in semiconductor manufacturing contexts.
The Austin Semiconductor Ecosystem — IP Strategy for a Competitive Market
Austin is a significant semiconductor market — home to major fabs including Samsung Austin Semiconductor, major design operations including NXP Semiconductors, Dell Technologies, and IBM, and a growing ecosystem of semiconductor design startups and fabless companies that are developing the next generation of AI accelerators, power management ICs, and specialty semiconductor solutions.
This competitive density creates specific IP strategy considerations for Austin semiconductor companies that differ from the considerations facing companies in less competitive geographic markets. When Samsung, NXP, and a dozen venture-backed design startups are all working in adjacent technology spaces in the same city, the patent landscape is both a competitive threat and a competitive opportunity — and navigating it requires systematic attention to both freedom to operate and patent portfolio building.
For fabless semiconductor companies — those that design chips without owning their own fabrication facilities — patent strategy centers primarily on circuit architecture and design patents, since the manufacturing process IP is owned by the foundry rather than the design company. The specific challenge for fabless companies is building patent portfolios that protect their design innovations without running into the extensive prior art held by major integrated device manufacturers and the foundries themselves. Prior art searching for fabless semiconductor company patent applications needs to cover not just publicly available patents but the extensive prior art embedded in industry standards documents, JEDEC and IEEE standards publications, and the conference proceedings of ISSCC, VLSI, and similar semiconductor technical conferences.
For companies in Austin's semiconductor supply chain — equipment manufacturers, materials suppliers, and EDA tool developers — patent strategy involves a different competitive dynamic where the customers are sophisticated semiconductor companies with their own large patent portfolios and robust IP licensing programs. I advise semiconductor supply chain companies on patent portfolio strategies that provide both offensive and defensive value in customer relationships — building portfolios that create licensing leverage while providing freedom to operate assurance for the company's own products.
Semiconductor Patent Prosecution — What 17 Years Teaches You
Seventeen years of USPTO prosecution across semiconductor and electronics art units has taught me things about semiconductor patent prosecution that are not in any textbook — things about specific examiner tendencies in the 2800 and 2900 art units, about the prior art documents that semiconductor examiners consistently cite and how to distinguish them effectively, about the claim amendment strategies that consistently advance prosecution without unnecessarily limiting claim scope, and about the examiner interview approaches that work in technical discussions with semiconductor-trained examiners.
The USPTO examining corps for semiconductor and electronics applications includes some of the most technically sophisticated examiners in the USPTO — practitioners with engineering degrees in electrical engineering, physics, and materials science who have developed deep technical expertise in their specific examination areas through years of reviewing the most advanced semiconductor patents filed by the world's leading technology companies. Engaging these examiners effectively requires the same kind of technical peer conversation that my engineering background enables — not just legal argument, but technically credible explanation of why the claimed innovation is genuinely novel and non-obvious over the cited prior art.
For semiconductor clients — whether established companies with large internal IP departments seeking outside prosecution counsel for specific technology areas, or startups building their first semiconductor patent portfolios — I offer the combination of genuine technical depth and extensive prosecution experience that the most demanding semiconductor patent work requires. The quality difference between semiconductor patents drafted and prosecuted by technically experienced counsel and those drafted by counsel without semiconductor engineering background is measurable — in claim breadth, in the strength of the prosecution record, and in the portfolio's long-term value as a competitive and licensing asset.
Call or text (512) 293-0710, email sconnolly@austin-patent-attorney.com, or fill out the contact form to discuss your semiconductor or electronics patent needs.
[ Semiconductor & Electronics Patent FAQs — Austin, Texas ]
Question: What makes semiconductor patents different from other patents?
Answer: Semiconductor patents require an extremely high level of technical precision. The inventions involve complex physics, circuit architecture, and fabrication processes that most patent attorneys struggle to capture accurately. With 7 years of semiconductor industry engineering experience including laser lithography, and a physics degree from UT Austin, I understand chip design and fabrication at a fundamental level.
Question: Can I patent a circuit design or fabrication process?
Answer: Yes — novel circuit designs, architectures, and fabrication processes are all patentable as utility patents. Both the structure of the circuit and the method of its fabrication can be protected through carefully drafted claims. My laser lithography background gives me direct experience with the manufacturing processes that are often at the heart of semiconductor patent applications.
Question: Do I need a patent attorney with engineering experience for semiconductor patents?
Answer: For technically complex semiconductor inventions, yes — the quality of the patent depends directly on how well the attorney understands the technology. I spent over seven years as a manufacturing process engineer in the semiconductor industry before becoming a patent attorney. That experience translates directly into stronger patent claims and better protection for your IP.
Question: How do semiconductor companies, including Austin fabless startups, use continuation applications to maintain competitive patent coverage?
Answer: Major semiconductor companies — particularly in the memory and logic sectors — maintain long-running patent families with active pending continuation applications that allow them to pursue new claim sets as the competitive landscape evolves. A company that filed a patent application on a fundamental memory architecture in 2010 may still have continuation applications pending in 2026, pursuing claims directed at specific implementations of that architecture in products that did not exist in 2010 but that embody the same fundamental inventive concept. This strategy is especially valuable for fabless semiconductor companies, where the competitive landscape often evolves faster than individual patent prosecution timelines — a claim set optimally directed at today's competitive products may need to be redirected at tomorrow's implementations before prosecution concludes. I draft original semiconductor patent specifications with continuation strategy specifically in mind from the first filing — comprehensive technical disclosure that supports not just the current product's architecture but the broader inventive principle that will govern future implementations — so a fabless client's portfolio stays directed at current competitor products throughout its life rather than becoming technically obsolete as the market evolves.
Question: How do you patent a semiconductor innovation that was developed in collaboration with a foundry like TSMC or GlobalFoundries?
Answer: Collaborative development with a foundry creates specific IP ownership questions that need to be resolved before filing. The foundry's own process technology — their standard PDK, their baseline process flows, their proprietary materials and equipment configurations — is the foundry's confidential IP, and your patent application must describe your innovation without disclosing the foundry's confidential information. The foundry agreement's IP provisions determine who owns innovations developed jointly by your engineers and the foundry's process engineers — provisions that are frequently unfavorable to the fabless company if negotiated without IP counsel involvement. I advise clients on foundry agreement IP provisions before signing and ensure that patent applications covering innovations developed with foundry collaboration describe what is genuinely yours without creating disclosure risks for the foundry relationship.
Question: What is the specific prior art landscape challenge for advanced semiconductor packaging patents?
Answer: Advanced semiconductor packaging — 2.5D and 3D integration, chiplet architectures, through-silicon vias, fan-out wafer-level packaging — is one of the most densely patented technology areas in the semiconductor industry. The prior art landscape includes extensive portfolios from ASE, Amkor, TSMC, Intel, Samsung, and IMEC alongside significant academic literature from research institutions worldwide. Navigating this landscape requires searching not just the US patent databases but the extensive international filings — particularly from Korean, Taiwanese, and Japanese assignees — and the IEEE ECTC proceedings where packaging innovations are frequently first published. My approach to semiconductor packaging patent prosecution specifically covers this international and technical literature landscape rather than relying on US-centric patent database searches that miss the most relevant prior art.
Question: How does your experience with laser lithography specifically improve the quality of semiconductor process patents?
Answer: Laser lithography is the photolithographic patterning step that ultimately determines the minimum feature size achievable in semiconductor manufacturing — the step that more than any other determines whether a circuit architecture innovation is manufacturable at production scale. My seven years of direct experience with deep ultraviolet excimer laser systems, photoresist exposure and development chemistry, critical dimension measurement and control, and process-induced defect mechanisms gives me specific knowledge of the process constraints that define what semiconductor process innovations are genuinely novel and non-obvious. When a client brings me a semiconductor process patent matter I am not approximating my way through unfamiliar technology — I am working in a domain I know from direct fabrication floor experience. That familiarity is most evident in claim drafting: the specific process parameters, the critical physical mechanisms, and the performance measurements that define the inventive space are things I understand at an engineering peer level.
Question: What semiconductor patent considerations are specific to companies operating in Austin's Samsung Austin Semiconductor supply chain?
Answer: Companies in the Samsung Austin Semiconductor supply chain — equipment suppliers, materials companies, EDA tool providers, and design service companies serving Samsung's north Austin fab — have specific IP strategy considerations that reflect their relationship with a major semiconductor manufacturer. Supply agreements with Samsung may include IP provisions affecting who owns innovations developed specifically for Samsung's processes, what rights Samsung receives in the supplier's general IP, and what confidentiality obligations apply to process-specific technical information. Equipment and materials suppliers whose innovations are incorporated into Samsung's manufacturing process need patents that protect their innovations without disclosing Samsung's confidential process details. And the competitive intelligence value of understanding Samsung's patent filings — which signal their technology development direction — is directly relevant to supply chain companies building complementary innovations. I advise supply chain companies on IP strategy that navigates all of these considerations specifically.
Question: How do you approach prior art searching for a semiconductor invention when the most relevant prior art may be in Japanese or Korean patents?
Answer: Japanese and Korean patent offices — JPO and KIPO — have been at the forefront of semiconductor innovation for decades, and their patent databases contain extensive prior art that keyword-based English-language patent database searches miss entirely. JPO and KIPO filings are searchable through Espacenet and J-PlatPat with machine translation, but effective searching requires knowing the right classification codes — the CPC classifications for specific semiconductor device structures and process techniques — and evaluating machine-translated Japanese and Korean patent documents for technical relevance using genuine semiconductor engineering knowledge. My semiconductor engineering background specifically helps in this evaluation — recognizing when a machine-translated Japanese process patent describes the same physical mechanism as the claimed invention even when the terminology differs from the English-language prior art. For semiconductor applications where Japanese and Korean prior art is particularly relevant — memory, display technology, packaging, advanced logic — I extend searching specifically to these databases rather than relying on US-centric search strategies.
Question: What is the patent strategy for a semiconductor company that develops both standard-essential and non-essential innovations?
Answer: Managing a mixed portfolio of standard-essential patents — subject to FRAND licensing obligations — and non-essential patents requires deliberately different prosecution and licensing strategies for each category. SEPs that cover technology necessarily implemented by anyone practicing a relevant standard require FRAND licensing — which constrains the licensing leverage you can extract from them but provides guaranteed licensing demand from every implementer. Non-essential patents can be licensed selectively with commercially negotiated terms that reflect the specific value they provide to specific licensees. The critical strategic decision is prospective — identifying before or during standards-setting participation which innovations are candidates for standardization and which should be kept outside the standard to preserve non-FRAND licensing leverage. I advise semiconductor clients on this strategic distinction from the time of initial patent filing, not retroactively after standards decisions have been made.
Question: What makes a semiconductor process innovation patentable versus just a process optimization?
Answer: The line between a patentable process innovation and an unpatentable routine optimization is one of the most practically significant questions in semiconductor process patent prosecution. A genuine process innovation involves a non-obvious technical insight — a new physical mechanism being exploited, a new combination of process steps that achieves something not previously achievable, or a specific technical discovery about material behavior or process chemistry that enables a capability that did not exist before. A routine optimization — reducing a known process parameter by a few percent, choosing from among known alternatives — is likely obvious to a person of ordinary skill and not patentable. My semiconductor manufacturing engineering background helps me make this distinction accurately for the specific process innovations my clients bring to me, because I have worked with the process variables and understand what represents genuine technical insight versus incremental adjustment.
Question: Can I patent a semiconductor device structure that is an improvement on existing MOSFET designs?
Answer: Yes — novel improvements to MOSFET and other transistor structures are among the most actively patented innovations in the semiconductor industry. The dense prior art landscape of transistor design — including decades of university research, industry filings from companies like Intel, Samsung, TSMC, and IMEC, and the extensive IEEE technical literature — means that prior art searching must be thorough and that claim drafting must precisely distinguish the specific structural innovation from what already exists. But genuine novel transistor structure innovations — new gate geometries, novel channel materials, specific source-drain engineering approaches, novel gate stack compositions — remain patentable and competitively significant.
Question: How does semiconductor patent practice differ for fabless versus integrated device manufacturers?
Answer: Fabless semiconductor companies — those that design chips without owning their own fabrication facilities — build patent portfolios primarily around circuit architecture, design methodology, EDA innovations, and specific circuit implementations. They cannot patent the manufacturing processes used by their foundries. Integrated device manufacturers — companies like Intel, Samsung, and GlobalFoundries that both design and manufacture — can patent both their circuit designs and their proprietary fabrication processes, creating broader and deeper IP coverage. For fabless companies, I focus portfolio building on the circuit-level and system-level innovations that constitute genuine competitive differentiation, and I advise on how to structure claims that protect design innovations effectively without requiring disclosure of the foundry's confidential process information.
Question: What is the role of semiconductor standards in patent strategy?
Answer: Industry standards in semiconductor markets — from DRAM interface standards to wireless communication protocols to interconnect specifications — create both patent opportunities and complications. Standards-essential patents (SEPs) are patents that cover technology necessarily implemented by anyone practicing a standard. SEP holders typically must license on FRAND (fair, reasonable, and non-discriminatory) terms, limiting their licensing leverage compared to non-essential patents. For companies participating in standards-setting organizations, the disclosure and licensing obligations that SSO participation entails need to be understood before participating in standards development with proprietary technology. I advise semiconductor clients on how standards participation affects their IP strategy and how to maximize the value of both SEPs and non-essential patents in their technology space.
Question: Can I patent an integrated circuit layout?
Answer: IC layout designs — the specific physical arrangement of elements in an integrated circuit — have a specialized form of protection under the Semiconductor Chip Protection Act of 1984 that is distinct from patent protection. SCPA protection covers original mask work registrations and provides 10 years of protection from exploitation of the protected mask work. Patent protection for IC layouts is available for the underlying circuit architecture and can cover novel layout topologies if they embody non-obvious technical innovations beyond the circuit schematic level. Many companies pursue both SCPA registration and patent protection for significant IC layout innovations.
Question: What is a patent troll and how do I protect my company from one?
Answer: A patent assertion entity — colloquially called a patent troll — is a company that acquires patents with the primary purpose of licensing them aggressively or litigating against operating companies rather than practicing the technology. Protection against patent assertion entities involves both offensive and defensive measures: building your own patent portfolio to provide leverage in licensing negotiations, conducting freedom to operate analysis before product launches to identify potential exposure, and maintaining good prior art documentation that can support invalidity challenges if a weak patent is asserted against you. Inter partes review at the PTAB is currently the most effective tool for challenging the validity of weak patents asserted by trolls.
Question: How do I protect innovations in semiconductor packaging and advanced packaging?
Answer: Advanced semiconductor packaging — 2.5D and 3D integration, chiplet architectures, fan-out wafer-level packaging, and through-silicon via technology — is one of the most active areas of semiconductor patent activity, because packaging has become a primary driver of system performance as transistor scaling slows. Packaging innovations can be protected through utility patents on the specific integration approaches, the assembly processes, the interconnect architectures, and the thermal management solutions — as well as design patents on distinctive packaging structures. The prior art in advanced packaging involves significant contributions from OSATs like ASE and JCET, substrate suppliers, and the major IDMs, so thorough prior art searching is essential before filing.
Question: What should I know about semiconductor patent licensing pools and consortia?
Answer: Several important semiconductor technology areas are subject to patent licensing pools — coordinated licensing arrangements through which multiple patent holders license a collection of patents to implementers under a single agreement. Via Licensing, Avanci, and MPEG LA manage pools covering various wireless, video, and connectivity technologies implemented in semiconductors. For companies implementing technology covered by a pool, joining the pool's licensing program may be more efficient than negotiating individual licenses with each pool member. For companies whose patents cover pool-relevant technology, participating in the pool as a licensor can provide steady licensing income. I advise semiconductor clients on both the costs of implementing pool-covered technology and the opportunities for participating as licensors in relevant pools.
Question: Can a semiconductor process patent be valid if the process cannot be practiced commercially yet?
Answer: A patent does not require that the claimed invention be commercially viable or currently manufacturable at scale — only that it be enabled by the specification and useful in principle. Many semiconductor process patents cover innovations that represent extensions of current capability — processes that are technically feasible but not yet commercially optimized. The enablement requirement is satisfied if a person of ordinary skill could practice the invention based on the specification, even if significant additional engineering work is required to make it commercially practical. Research-stage semiconductor innovations often warrant patent protection precisely to establish priority while the commercial development work continues.
Question: How do I protect innovations in semiconductor characterization and metrology?
Answer: Semiconductor characterization and metrology tools — optical critical dimension measurement, overlay metrology, defect inspection, and thin film characterization — are critical enabling technologies for advanced chip manufacturing and represent significant patent territory. Innovations in metrology typically involve the physical measurement principle, the optical or particle beam system design, the signal processing algorithms, or the data analysis approaches. My optics background and semiconductor manufacturing experience — working with metrology tools as an end user — inform how I approach characterization and metrology patent prosecution with genuine technical understanding of what these systems actually do and what constitutes genuine technical innovation in this space.
Question: What is the impact of export controls on semiconductor patent strategy?
Answer: Export Administration Regulations and the Entity List designations that have restricted US semiconductor technology access for certain foreign companies have made the interaction between export controls and IP strategy increasingly important. A patent application that discloses controlled semiconductor technology — certain high-performance computing chips, advanced lithography technology, or specific semiconductor manufacturing equipment — may require export license review before the application can be published or shared with foreign associates for international prosecution. I advise semiconductor clients on the export control review process for patent applications and how to coordinate patent filing strategy with export compliance requirements.
Question: Can I protect innovations in semiconductor yield improvement?
Answer: Yield improvement innovations — specific process control approaches, defect reduction methodologies, or novel process monitoring techniques that increase the percentage of working chips per wafer — are valuable and patentable if they involve novel and non-obvious technical approaches rather than routine process engineering. My laser lithography process engineering experience specifically involved yield optimization work — understanding how process parameter variation affects feature quality and device yield — which gives me direct technical insight into what constitutes genuine innovation in yield improvement versus routine process engineering practice.
Question: How do I protect semiconductor IP that was jointly developed with a university research partner?
Answer: Joint development with university research partners creates IP ownership complications specific to the academic context. If the research was federally funded, Bayh-Dole Act provisions apply — giving the university the right to elect title to inventions made under the federal award. If the development was industry-sponsored without federal funding, the IP ownership terms negotiated in the sponsored research agreement govern. I advise semiconductor companies on negotiating sponsored research agreements with UT Austin and other Texas research institutions to ensure that the company receives adequate IP rights to justify its research investment while satisfying the university's technology transfer obligations.
Question: What is a freedom to operate analysis specifically for semiconductor products?
Answer: FTO analysis for semiconductor products is more complex than for most other technology areas because the semiconductor IP landscape is extraordinarily dense — major companies hold patent portfolios numbering in the tens of thousands, and the relevant art units have decades of prior filings. A comprehensive semiconductor FTO analysis must cover circuit architecture patents, fabrication process patents, package and integration patents, standards-essential patents, and software patents covering the chip's firmware and control software. The analysis requires genuine technical understanding of both the product being analyzed and the claims of potentially relevant patents — which is where my semiconductor engineering background directly improves the accuracy and reliability of the FTO conclusions I provide.
Question: Can I patent innovations specifically related to EUV lithography?
Answer: EUV lithography — the current leading-edge patterning technology using 13.5nm extreme ultraviolet light — is one of the most heavily patented technology areas in the semiconductor industry, dominated primarily by ASML and its technology partners including Zeiss for optics and Cymer for light sources. Genuine innovations in EUV — new photoresist chemistries, novel mask architectures, specific source-collector optimization approaches, new computational lithography methods specifically adapted for EUV — are patentable if novel and non-obvious over the existing dense prior art. My deep ultraviolet lithography engineering background provides the photolithographic physics foundation that makes me effective at evaluating EUV-related innovations, even as EUV represents an advancement beyond the DUV systems I worked with directly.
Question: What are the most important semiconductor patent cases I should know about?
Answer: Several Federal Circuit and Supreme Court decisions have significantly shaped semiconductor patent practice. SRAM LLC v. CIF Licensing established important precedents about FRAND licensing obligations. The Tessera Technologies licensing campaigns demonstrated how packaging innovation patents can generate significant licensing revenue. The Rambus DRAM litigation established the boundaries of standards-essential patent assertion. More recently, the Netlist v. Samsung and Netlist v. Google litigation involves memory interface patents with significant industry implications. For substantive patent law, the Alice decision affects software claims in semiconductor control systems, and the WD Cal and Delaware district court semiconductor patent decisions shape litigation strategy. I follow significant semiconductor patent litigation closely because the outcomes directly affect prosecution strategy for new applications.
Question: How do I protect innovations in semiconductor design automation and EDA tools?
Answer: Electronic design automation innovations — novel place-and-route algorithms, new simulation methodologies, specific approaches to timing closure, or novel DRC/LVS verification methods — sit at the intersection of software patent practice and semiconductor engineering. EDA tool patents must navigate Alice/Mayo for the algorithmic components while leveraging the technical specificity of the semiconductor design context — the specific physics of electronic circuits, the specific constraints of manufacturable designs, and the concrete computational improvements that novel EDA approaches achieve. My combination of semiconductor engineering experience and software patent prosecution capability makes me effective at protecting EDA innovations that require understanding both the algorithm and the semiconductor physics it operates on.
Question: What is the patent landscape for neuromorphic computing and in-memory computing?
Answer: Neuromorphic computing — architectures that mimic biological neural processing — and in-memory computing — performing computation within memory arrays to reduce data movement — represent two of the most actively developing frontiers in semiconductor architecture patent activity. Both areas involve significant patent activity from IBM, Intel, Samsung, and academic research institutions, with growing activity from startups. Genuine innovations in neuromorphic circuit design, in-memory computing array architecture, novel synaptic device designs, or specific training algorithms adapted for neuromorphic hardware can be patentable with proper claim drafting that distinguishes from the growing prior art base. I am actively developing expertise in these emerging architecture areas.
[ Related Services ]
Clients protecting semiconductor innovations often also work with me on:
[Software & AI Patents] · [PCT International Patents] · [Freedom to Operate Opinions] · [Patent Portfolio Management] · [Of Counsel Services for Foreign Applicants]
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Semiconductor & Electronics Patent Services
I want to be direct about what my semiconductor engineering background means for your patent and why it is genuinely different from the credentials most patent attorneys present. I spent over seven years on the manufacturing floor of a semiconductor fab as a process engineer specializing in laser lithography — the photolithographic process that patterns nanoscale features on integrated circuits using deep ultraviolet excimer lasers. That experience gave me working knowledge of semiconductor physics, photoresist chemistry, process control, yield engineering, and the fabrication-design interaction that determines how circuit innovations become manufacturable products. When you describe your circuit architecture innovation, your novel fabrication process, your new device structure, or your advanced packaging approach, I understand what you are describing at an engineering peer level — not as an intelligent legal professional interpreting a technical briefing, but as someone who has worked in the same environment with the same physics. That starting point produces measurably better semiconductor patents — more comprehensive prior art searches that cover the IEEE and conference literature where the most relevant prior art for advanced semiconductor innovations is concentrated, more technically accurate specifications that satisfy the enablement requirement for complex multi-layer device inventions, more precise claim language that captures the genuine novelty of your circuit or process innovation rather than a surface description of it, and more technically credible prosecution arguments that resonate with USPTO examiners who are themselves trained electrical engineers.
I work with the full range of Austin's semiconductor ecosystem — from fabless chip design startups developing AI accelerator architectures to semiconductor equipment companies protecting novel lithography and etch innovations to established device manufacturers protecting advanced memory and logic architectures. I also work with the semiconductor supply chain — EDA tool developers, materials innovators, and packaging companies whose IP strategy requires understanding how their innovations interact with the competitive portfolios of their major customers.
If you have a semiconductor or electronics innovation to protect, I offer a free 30-minute phone consultation to discuss your specific technology, assess the prior art landscape at a high level, and explain what strong semiconductor patent protection would realistically look like for your invention.
Call or text (512) 293-0710, email sconnolly@austin-patent-attorney.com, or fill out the form. Consultations are available Monday through Friday, 1:00pm to 4:00pm Central Time.
All consultations are confidential under attorney-client privilege. No obligation.
Phone: 512-293-0710
Email: sconnolly@austin-patent-attorney.com
Location: Austin, Texas
Serving Austin, Round Rock, Cedar Park, Georgetown, and all of Central Texas.
USPTO matters are federal — I work with clients throughout Texas and nationwide.